www.iterrac.com IT4032D 50-ps wideband phase delay with 180-deg. flipper (advanced information) this is an advanced data sheet. see ?product status definitions? on web site or catalog for product development status. october 5, 2005 doc. 4036 rev 0 1 iterra communications 2400 geng road, ste. 100, palo alto, ca 94303 phone (650) 424-1937, fax (650) 424-1938 description features the IT4032D is an ultra-wideband phase delay fabricated using 0.1- m hbt gaas technology. the high output voltage, excellent rise and fall times, and the high eye diagram quality at all data rates up to 12.5 gb/s makes the IT4032D suit able for timing adjustment in data and clock distribution at a very high speed. complex digita l applications that can benefit from the IT4032D include clock data recovery, edge detectors , nrz/rz converters, mux/demux, and data restoration it is based on an ecl topology in order to guarantee high-speed operation. the device features a single delay el ement that provides up to 50 ps delay and a 180 deg. shift capability. the delay control can be either differential (using both vcp and vcm) or single-ended (vcp is the active control pad while vcm is shorted to vcref). the nominal control voltage range for the delay is from -2.2 v to -3.0 v, whether t he control is single-ended or differential. the flipping control can be either differential (using both vfp and vfn), or single-ended (vfp is the active control pad while vfm is shorted to vcre f). the nominal control voltage for the flipping is -2.2 v or -3.0 v whether the control is single -ended or differential. the device is capable of delaying nrz streams with a data rate up to 12.5 gb/s or a clock signal with frequency up to 10.7 ghz. the inputs and the output s are dc coupled. at the input side the internal 50-ohm resistors avoid the need for external imped ance matching terminations. the IT4032D uses scfl i/o levels and is designed so to allow for either single ended or differential data input. ? wideband signal handling: up to 12.5 gb/s nrz ? delay adjustment: to 50 ps ? flipping capability (180 deg. shift) ? 900 mvpp typical single-ended output ? jitter rms: <1.5 ps device diagram ? output rise time (20% ? 80 %): <22 ps ? output fall time (20% ? 80 %): <20 ps ? 50-ohm matched dc-coupled inputs and outputs ? differential or single-ended i/o ? power consumption: 1.15 w
www.iterrac.com IT4032D 50-ps wideband phase delay with 180-deg. flipper (advanced information) this is an advanced data sheet. see ?product status definitions? on web site or catalog for product development status. october 5, 2005 doc. 4036 rev 0 2 iterra communications 2400 geng road, ste. 100, palo alto, ca 94303 phone (650) 424-1937, fax (650) 424-1938 timing diagram absolute maximum ratings c 150 -65 storage temperature t stg c 125 -15 operating temperature range ? die t a v 0 -5.0 flipping control voltage vf v 0 -5.0 delay control voltage vc v 1.5 -1.5 input voltage level, low level v il v 1.5 -1.5 input voltage level, high level v ih v 0 -5.5 power supply voltage v ee units max. min. parameters/conditions symbol v -0.45 dc input voltage (with dc-coupled input) v indc v -0.9 input voltage level, low level (single ended) v il v 0.0 input voltage level, high level (single ended) v ih v -2.2 -3.0 flipping control voltage vf v -2.2 -2.6 -3.0 delay control voltage vc v -5 power supply voltage v ee c 85 0 operating temperature range ? die t a units max typ. min. parameters/conditions symbol recommended operational conditions stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this document is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability.
www.iterrac.com IT4032D 50-ps wideband phase delay with 180-deg. flipper (advanced information) this is an advanced data sheet. see ?product status definitions? on web site or catalog for product development status. october 5, 2005 doc. 4036 rev 0 3 iterra communications 2400 geng road, ste. 100, palo alto, ca 94303 phone (650) 424-1937, fax (650) 424-1938 electrical characteristics w 1.15 power dissipation p d ma 230 power supply current i ee ps 1.5 rms jitter (5) j rms ps 9 peak-to-peak jitter (5) j p-p ghz 10.7 maximum clock frequency f max db 8 output return loss (up to 15 ghz) s 22 db 23 input return loss (up to 15 ghz) s 11 ps 50 output phase delay adjustment (4) t adj ps 180 output delay high-low transition (4) td l ps 180 output delay low-high transition (4) td h ps 20 output fall time (20% ? 80%) t f ps 22 output rise time (20% ? 80%) t r v 1.0 0.9 0.8 data output voltage amplidude (3) v out v -0.45 dc input voltage (with dc-coupled input) (2) v indc v -0.9 input voltage level, low level (single ended) v il v 0.0 input voltage level, high level (single ended) v ih v -5.25 -5.00 -4.5 power supply voltage v ee units max typ min parameters symbol 1. electrical characteristics at ambient temperature. 2. in case of single- ended input the unused pin has to be tied to vindc. 3. in case of single- ended output, the unused pad must be terminated with 50 ohms to ground. 4. refer to timing diagram. 5. on a 10.7 gb/s prbs pattern. eye diagram performance die measurement die measurement vee: -5.0 v input data rate: 10.7 gb/s vee: -5.0 v input data rate: 10.7 gb/s single-ended data input: +/-450 mvpp single-ended data input: +/-450 mvpp control voltage: vcm= vfm =vcref control voltage: vcm=vfm=vcref; vcp=-2.2 v; vfp=-3.0 v vcp =-3.0 v; vfp =-3.0 v
www.iterrac.com IT4032D 50-ps wideband phase delay with 180-deg. flipper (advanced information) this is an advanced data sheet. see ?product status definitions? on web site or catalog for product development status. october 5, 2005 doc. 4036 rev 0 4 iterra communications 2400 geng road, ste. 100, palo alto, ca 94303 phone (650) 424-1937, fax (650) 424-1938 eye diagram performance (cont.) die measurement vee: -5.0 v input data rate: 12.5 gb/s single-ended data input: +/-450 mvpp control voltage: vcm=vfm=vcref; vcp=-2.2 v; vfp=-3.0 v die measurement vee: 5.0 v input data rate: 12.5 gb/s single-ended data input: +/-450 mvpp control voltage: vcm=vfm=vcref; vcp=-2.2 v to -3 v (a ccumulating); vfp=-3.0 v die measurement vee: -5.0 v input data rate: 12.5 gb/s single-ended data input: +/-450 mvpp control voltage: vcm=vfm=vcref; vcp=-2.2 v; vfp=-3.0 v die measurement vee: 5.0 v input data rate: 10.7 gb/s single-ended clock input: +/-450 mvpp control voltage: vcm=vfm=vcref; vcp=-2.2 v to -3 v (a ccumulating); vfp=-3.0 v
www.iterrac.com IT4032D 50-ps wideband phase delay with 180-deg. flipper (advanced information) this is an advanced data sheet. see ?product status definitions? on web site or catalog for product development status. october 5, 2005 doc. 4036 rev 0 5 iterra communications 2400 geng road, ste. 100, palo alto, ca 94303 phone (650) 424-1937, fax (650) 424-1938 recommended operational setup chip size 2235 m 10 m x 1400 m 10 m chip thickness: 104 m 3 m pad size: 100 m x 100 m rf pad pitch: 150 m recommended chip mounting
www.iterrac.com IT4032D 50-ps wideband phase delay with 180-deg. flipper (advanced information) this is an advanced data sheet. see ?product status definitions? on web site or catalog for product development status. october 5, 2005 doc. 4036 rev 0 6 iterra communications 2400 geng road, ste. 100, palo alto, ca 94303 phone (650) 424-1937, fax (650) 424-1938 pad positions and dimensions chip size: 2235 m 10 m x 1400 m 10 m chip thickness: 104 m 3 m pad size: 100 m x 100 m rf pad pitch: 150 m
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